Research

Research Overview

My research focuses on scalable optimization and high-performance computing for electronic design automation (EDA). I develop algorithms and systems that improve the efficiency, quality, and robustness of VLSI physical design, with current emphasis on 3D IC physical design and GPU acceleration.

3D IC Physical Design

3D IC integration offers a promising path to shorter interconnects, higher bandwidth, and heterogeneous integration, while introducing fundamentally new physical design challenges across stacked dies. My research focuses on native 3D physical design, developing scalable analytical and combinatorial optimization methods for 3D placement, legalization, routing, and timing-driven optimization, with explicit modeling of 3D integration constraints.

3D placement case study from ICCAD 2022 — Die-to-die 3D placement

3D macro placement case study from ICCAD 2023 — Heterogeneous 3D mixed-size placement

3D global routing example — Heterogeneous-resource-aware 3D routing

Selected Publications

[C12] Yuhao Ji, Yunqi Shi, Tianshu Hou, Yuxuan Zhao, Chunyuan Zhao, Peiyu Liao, Zizheng Guo, Chao Qian, Yibo Lin, Bei Yu, “Integrated Timing-driven Placement for Hybrid-Bonding-based Face-to-Face 3D ICs”, ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026.

[C11] Lancheng Zou, Sing Sen YE, Shuo Yin, Yuan Pu, Jiaxi Jiang, Siting Liu, Yuxuan Zhao, Bei Yu, “IncreMacro-3D: Incremental Macro Placement for Face-to-Face Stacked Memory-on-Logic 3D ICs”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Verona, Italy, Apr. 20–22, 2026. (PDF)

[C7] Yuxuan Zhao, Feng Gu, Siting Liu, Peiyu Liao, Bei Yu, “H3D: Heterogeneous Resources Aware Global Router for Face-to-Face Bonded 3D ICs”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Oct. 26–30, 2025. (PDF)

[C6] Yuxuan Zhao, Peiyu Liao, Bei Yu, “3D-Flow: Flow-based Standard Cell Legalization for 3D ICs”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 22–25, 2025. (PDF)

[J2] Yuxuan Zhao*, Peiyu Liao*, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu, “Analytical Heterogeneous Die-to-Die 3D Placement with Macros”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024. (PDF)(Binary)

[J1] Peiyu Liao*, Yuxuan Zhao*, Dawei Guo, Yibo Lin, Bei Yu, “Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023. (PDF)(Binary)

GPU Acceleration

GPU acceleration is essential for scaling modern EDA and machine learning workloads, but effective acceleration requires more than simply porting algorithms to parallel hardware. My research develops GPU-friendly formulations, graph transformations, and parallel kernels that transform irregular optimization problems into efficient, hardware-aware computation across a broad range of applications.

GPU execution structure — GPU accelerated 3D placement

Divergence theorem example for density gradient accumulation — Divergence-theorem acceleration

Selected Publications

[C8] Peiyu Liao*, Yuxuan Zhao*, Siting Liu, Bei Yu, “Ultrafast Density Gradient Accumulation in 3D Analytical Placement with Divergence Theorem”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Oct. 26–30, 2025. (PDF)

[J2] Yuxuan Zhao*, Peiyu Liao*, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu, “Analytical Heterogeneous Die-to-Die 3D Placement with Macros”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024. (PDF)(Binary)

[J1] Peiyu Liao*, Yuxuan Zhao*, Dawei Guo, Yibo Lin, Bei Yu, “Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023. (PDF)(Binary)

[C3] Yuxuan Zhao, Qi Sun, Zhuolun He, Yang Bai, Bei Yu, “AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution”, AAAI Conference on Artificial Intelligence (AAAI), Feb. 7–14, 2023. (Oral) (PDF)

[C2] Qi Sun, Xinyun Zhang, Hao Geng, Yuxuan Zhao, Yang Bai, Haisheng Zheng, Bei Yu, “GTuner: Tuning DNN Computations on GPU via Graph Attention Network”, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Jul. 10–14, 2022. (PDF)

[C1] Haoyu Yang, Kit Fung, Yuxuan Zhao, Yibo Lin, Bei Yu, “Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Mar. 14–23, 2022. (PDF)